It is a module about VLSI, where student are supposed to design something(specified by the lecturer) on cadence.
For my semester, my group was made to design an Analog to Digital Converter(ADC). The premise of the project is that this device would be used in an ECG. So what the system would do is to take in the small signal, amplify it and then convert the analog signal into a digital signal.
Since the frequency of heart rate isn't exactly fast, we are looking at about 100++ Hz (engineers are not very specific unless required) and a resolution of about 10 bits. Below is the reconstructed sinewave after input a sine signal into its input.
So workload for our group was separated into 2 sub-groups. One person to design the Operational Transconductance Amplifer(OTA) and 2 other people to design the ADC. The ADC works based on Successive Approximation logic (SA).
How it works?
Well, when the signal goes into the ADC, a sample and hold block in the circuit will hold the signal. The input of the signal would be pass through a comparator which would compare this signal against a Digital to Analog Converter(DAC). The output of the comparator is passed into a Successive Approximation Register(SAR) which would determine the control logic of the DAC. The DAC is just a capacitor array which tries to convert the digitalised values of the SAR to an analog value so as to be used for comparison.
I was assigned to design the comparator and the DAC. I doubt there is any need to discuss about the DAC since it is just a capacitor array and a switch array. The only thing to note is to do the layout in common centroid to reduce capacitor mismatch. Layout is something that is not sufficiently taught in this module. Plug and play is sufficient to get your device working, but in the industry, drawing layout is a skill.
Design of a comparator
I'll just talk about it for a while.
Well, from the shallowest of levels looking at it, an analog comparator should be able to compare 2 inputs and determine if A is larger than B and appropriately produce a high or low output accordingly.
So we need to note the resolution of the comparator as well as the bandwidth. A 10 bit comparator should at least be able to to detect a difference of Full-scale/2^10, so as to appropriate digital output. That is resolution. Bandwidth is that it should be able to work at the required frequency that you need.
A simple comparator usually have 3 stages. Pre-amplifier, latch and buffer. The pre-amplifier is important due to issues such as metastability as well as kickback. Maybe I should just discuss that first.
Metastability is an issue pertaining to the latch of the comparator. It occurs when the latch is unable to latch onto a high or a low. So how the pre-amp solves this is by providing a gain into the input to increase the initial voltage so as to help the latch to reach its high or low state faster. Other ways to reduce this is to reduce the length of the MOSFETs, else we can use a double latch. But Metastability is not really an issue in EE4410 since the minimum clock time is 5kHz, which is quite low.
Upon evaluation(evalutation being like testing the real fabricated chip), our comparator can work even at 50KHz(I sure remember it can work at 80kHz, but overcommiting is bothersome).
Kickback, on the other hand is one royal pain in the ass. But learning how to solve the kickback would improve your INL and DNL and you would really learn how to design a pre-amp(impt clue). Since power consumption is an issue in EE4410, using a synchronous comparator, sure cuts down the power consumed, but it comes at a price of complication in the form of kickback.
Anyway, getting back to pre-amp, its usually just a differential with maybe a common source amplifier connected afterwards. The next stage being the latch is use to pull the output up or down based on the differential output. Its a rather simple design so really nothing much to talk about it. The final stage is the buffer. Nothing much, since its just a digital buffer, think of it as 2 inverters used to pull the output from the latch.
Looking back, it was a hectic but fun module. The GA was helpful, but they cannot tell you very much(otherwise they might as well do it for you). The first sem is usually very time consuming and stressful. The next sem is usually better because it only left to testing the circuit.
I better get back to my work. I am trying to figure out how to design a charge pump...seriously no idea...haha...
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